Slack (Used in connection with timing)
In the world of FPGAs “Slack” is often used as a value describing if an implementation is meeting the timing constrains or not. If the value is positive timing constrains have been met. If it is negative, you need to work a bit more on your design to meet timing constrains.
Another way of saying it is, that this is the time difference between the expected signal’s arrival times to actual time taken by a signal to reach destination path.If the value is positive timing constrains have been meet. If it is negative timing is not met
– Set-up Slack: is the margin by which setup time is met.
– Hold Slack: is the margin by which hold time requirement is met.
Then difference in time of when different logic elements see the rising edge of the clock.
Set-up time: The signal to be sampled by a clock should be held for this time before the clock edge
The signal to be sampled by a clock should be held for this time after the clock edge.
The variation by which the clock period can vary from the reference clock. In the figure below, the blue line indicates the optimal/correct clock, and the markings in red the possible jitter.